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#risc-v (30 Repositories)

Ranked open-source repositories tagged with #risc-v, scored by pull request acceptance likelihood and maintainer engagement velocity.

Topic Avg Merge Rate

68.7%

Avg Review Latency

25.6h

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30 repositories tagged #risc-v

S TierBIBitBake 442

riscv/meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

80.0%
Merge Rate
2h
First Review
50%
1st-Timers
10
Maintainers
A TierC 347

OpenXiangShan/NEMU

Super fast RISC-V ISA emulator for XiangShan processor

70.7%
Merge Rate
19h
First Review
64%
1st-Timers
13
Maintainers
A TierRust 128

matter-labs/zksync-airbender

RISC-V prover system for ZKsync OS

79.7%
Merge Rate
10d
First Review
67%
1st-Timers
7
Maintainers
A TierC++ 693 7 GFIs

OFFTKP/felix86

Run x86 and x86-64 games on RISC‑V Linux

85.3%
Merge Rate
7d
First Review
100%
1st-Timers
2
Maintainers
A TierC++ 2.0k 1 GFIs

simdutf/simdutf

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers, Ghostty and Bun.

70.7%
Merge Rate
-
First Review
63%
1st-Timers
10
Maintainers
A TierScala 7.3k

OpenXiangShan/XiangShan

Open-source high-performance RISC-V processor

60.4%
Merge Rate
-
First Review
55%
1st-Timers
43
Maintainers
A TierC++ 2.9k

gem5/gem5

The official repository for the gem5 computer-system architecture simulator.

67.9%
Merge Rate
2d
First Review
55%
1st-Timers
45
Maintainers
A TierRuby 209

riscv/riscv-unified-db

Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools

48.8%
Merge Rate
1d
First Review
43%
1st-Timers
37
Maintainers
B TierScala 110

carlosedp/chiselv

A RISC-V Core (RV32I) written in Chisel HDL

100.0%
Merge Rate
<1h
First Review
100%
1st-Timers
2
Maintainers
A TierASAssembly 3.1k

openhwgroup/cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

25.4%
Merge Rate
6h
First Review
40%
1st-Timers
29
Maintainers
B TierScala 2.4k

ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

47.2%
Merge Rate
-
First Review
20%
1st-Timers
10
Maintainers
A TierC++ 1.1k

libriscv/libriscv

The fastest RVA23 RISC-V sandbox

86.2%
Merge Rate
-
First Review
50%
1st-Timers
2
Maintainers
B TierJavaScript 341

ESEO-Tech/emulsiV

A visual simulator for teaching computer architecture using the RISC-V instruction set

100.0%
Merge Rate
-
First Review
100%
1st-Timers
0
Maintainers
B TierC++ 111

cartesi/machine-emulator

The off-chain implementation of the Cartesi Machine

52.6%
Merge Rate
13h
First Review
50%
1st-Timers
2
Maintainers
B TierC 496

bouffalolab/bouffalo_sdk

BouffaloSDK is the IOT and MCU software development kit provided by the Bouffalo Lab Team, supports all the series of Bouffalo chips. Also it is the combination of bl_mcu_sdk and bl_iot_sdk

75.0%
Merge Rate
1h
First Review
100%
1st-Timers
0
Maintainers
B TierCMCMake 104

iarsystems/cmake-tutorial

Build and test embedded software using the IAR C/C++ Compiler alongside CMake

100.0%
Merge Rate
-
First Review
100%
1st-Timers
0
Maintainers
B TierC 560

eclipse-embed-cdt/eclipse-plugins

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

100.0%
Merge Rate
-
First Review
100%
1st-Timers
0
Maintainers
B TierTypeScript 343

Specy/asm-editor

An app to write, run and learn M68K, MIPS, RISC-V, X86, Z80 assembly

87.5%
Merge Rate
-
First Review
100%
1st-Timers
0
Maintainers
B TierVEVerilog 1.4k

chili-chips-ba/wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

100.0%
Merge Rate
9h
First Review
0%
1st-Timers
2
Maintainers
B TierRust 383 3 GFIs

zinnia-os/zinnia

Modular Unix-like 64-bit kernel

75.0%
Merge Rate
3h
First Review
0%
1st-Timers
2
Maintainers
B TierScala 150 2 GFIs

aesc-silicon/ElemRV

ElemRV - End-to-end Open-Source RISC-V Microcontroller

82.6%
Merge Rate
-
First Review
0%
1st-Timers
2
Maintainers
B TierScala 1.1k

firesim/firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

100.0%
Merge Rate
-
First Review
0%
1st-Timers
1
Maintainers
B TierASAssembly 710

openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

75.0%
Merge Rate
2d
First Review
0%
1st-Timers
3
Maintainers
B TierRust 426

emproof-com/nyxstone

Nyxstone: assembly / disassembly library based on LLVM, implemented in C++ with Rust and Python bindings, maintained by emproof.com

80.0%
Merge Rate
<1h
First Review
100%
1st-Timers
0
Maintainers
B TierGo 390

PentHertz/RF-Swift

🚀 A powerful multi-platform RF toolbox that deploys specialized radio, hardware, and other security tools in seconds on Linux, Windows, and macOS - supporting x86_64, ARM64 (Raspberry Pi, Apple Silicon), and RISC-V architectures without disrupting your primary OS. 📡✨

66.7%
Merge Rate
-
First Review
100%
1st-Timers
0
Maintainers
B TierVEVerilog 1.1k

Wren6991/Hazard3

3-stage RV32IMACZb* processor with debug

50.0%
Merge Rate
1d
First Review
0%
1st-Timers
1
Maintainers
B TierRust 111

Gaok1/Raven-RiscV

RISC-V simulator and IDE for learning assembly — RV32IMF, step-by-step debugger,cache , pipeline, multi-core simulator

0.0%
Merge Rate
-
First Review
0%
1st-Timers
1
Maintainers
B TierC++ 635

cvut/qtrvsim

RISC-V CPU simulator for education purposes

50.0%
Merge Rate
3d
First Review
0%
1st-Timers
0
Maintainers
B TierRORobotFramework 3.0k

renode/renode

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

20.0%
Merge Rate
<1h
First Review
0%
1st-Timers
2
Maintainers
B TierC 305

x-heep/x-heep

eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V

25.0%
Merge Rate
5d
First Review
0%
1st-Timers
0
Maintainers