#risc-v (30 Repositories)
Ranked open-source repositories tagged with #risc-v, scored by pull request acceptance likelihood and maintainer engagement velocity.
49.3%
44.2h
30 repositories tagged #risc-v
OFFTKP/felix86
Run x86 and x86-64 games on RISC‑V Linux
libriscv/libriscv
The fastest RVA23 RISC-V sandbox
simdutf/simdutf
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers, Ghostty and Bun.
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
ESEO-Tech/emulsiV
A visual simulator for teaching computer architecture using the RISC-V instruction set
Verilean/sparkle
A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.
openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
gem5/gem5
The official repository for the gem5 computer-system architecture simulator.
cartesi/machine-emulator
The off-chain implementation of the Cartesi Machine
carlosedp/chiselv
A RISC-V Core (RV32I) written in Chisel HDL
aesc-silicon/ElemRV
ElemRV - End-to-end Open-Source RISC-V Microcontroller
OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
cvut/qtrvsim
RISC-V CPU simulator for education purposes
LoveLonelyTime/Bergamot
An exquisite superscalar RV32GC processor.
riscv/riscv-unified-db
Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools
Gaok1/Raven-RiscV
RISC-V simulator and IDE for learning assembly — RV32IMF, step-by-step debugger,cache , pipeline, multi-core simulator
diodesign/diosix
A lightweight, robust, multiprocessor bare-metal hypervisor written in Zig for RISC-V
firesim/firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
eclipse-embed-cdt/eclipse-plugins
The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
popovicu/zig-time-sharing-kernel
Minimal implementation of a time-sharing kernel on RISC-V, implemented in Zig, on top of OpenSBI
standardsemiconductor/lion
Where Lions Roam: RISC-V on the VELDT
krillclaw/KrillClaw
The world's smallest AI agent runtime. 49KB. Written in Zig. Zero dependencies.
bouffalolab/bouffalo_sdk
BouffaloSDK is the IOT and MCU software development kit provided by the Bouffalo Lab Team, supports all the series of Bouffalo chips. Also it is the combination of bl_mcu_sdk and bl_iot_sdk
SingularityKChen/dl_accelerator
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
pulp-platform/mempool
A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
vproc/vicuna
RISC-V Zve32x Vector Coprocessor
OpenXiangShan/NEMU
Super fast RISC-V ISA emulator for XiangShan processor
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
beehive-lab/Maxine-VM
Maxine VM: A meta-circular research VM