aesc-silicon/ElemRV

Labels: documentation, bug, good first issue Difficulty: easy — a five-minute fix and a good first contribution. Problem The pin multiplexer table in docs/source/nonmetals/elemrv_h.rst (around line 184) disagrees with the RTL from pin 3 onwards. Every entry from there down is shifted by one. The RTL is authoritative — addPinmuxOption in hardware/scala/elemrv_h/ElemRV.scala:95-106: Pin Function 0 Function 1 Docs currently say 0-2 gpio0_0/pwm0_out_0, gpio0_1/pio0_0, gpio0_2/pio0_1 correct 3 uart0_tx gpio0_3 gpio0_3 / pio0_2 4 uart0_rx gpio0_4 uart0_tx / gpio0_4 5 uart0_cts gpio0_5 uart0_rx / gpio0_5 6 uart0_rts gpio0_6 uart0_cts / gpio0_6 7 gpio0_7 pwm0_comp_0 uart0_rts / gpio0_7 8 gpio0_8 i2c0_scl gpio0_8 / pwm0_comp_0 9 gpio0_9 i2c0_sda gpio0_9 / i2c0_scl 10 gpio0_10 i2c0_interrupt_0 gpio0_10 / i2c0_sda 11 gpio0_11 pio0_2 gpio0_11 / i2c0_interrupt_0 The board's own pinctrl definitions agree with the RTL, so it is only the table that is wrong — but it

Labels: documentation, good first issue Difficulty: easy Problem docs/source/nonmetals/ contains elemrv_h.rst and elemrv_c.rst, and the toctree in index.rst lists exactly those two. There is no elemrv_n.rst — ElemRV-N, the most capable nonmetal SoC and the one with HyperRAM, a data cache and branch prediction, is undocumented. What to do Add docs/source/nonmetals/elemrv_n.rst following elemrv_h.rst, and add it to the toctree. Take every value from the RTL, not from the other pages: CPU configuration — VexiiRiscvCoreParameter.performance(...) in zibal/hardware/scala/zibal/platform/nonmetals/Nitrogen.scala: ISA string, cache sizes, BTB sets, PMP regions. Clock domains and frequencies from hardware/scala/elemrv_n/SG13CMOS5L/SG13CMOS5L.scala — note that Nitrogen has five (system, debug, hyperbus, xip, peripheral), unlike H's two. Memory map from Nitrogen.scala: OCRAM, HyperRAM cached and uncached windows, SPI flash, peripherals. Peripheral list, interrupt numbers and error-source nu

Labels: documentation, good first issue Difficulty: easy — but only useful if done on a genuinely clean machine. Problem Nobody has confirmed that a newcomer can get from git clone to a running SoC without prior knowledge of the project. The flow involves Google's repo for the manifest, a podman container, task as the entry point, and a Renode emulation — each fine on its own, unusual in combination, and none of it obvious. The most valuable thing this project can offer a curious visitor is a running RISC-V SoC with a blinking LED in fifteen minutes, no FPGA required. That path exists — task baremetal:compile then task sim:emulate — but it is not written down as a single verified sequence, and it is not known whether it works from scratch. What to do On a machine (or fresh VM/container) with nothing installed: Follow the current README.rst and docs/source/installation.rst literally — no fixing things from memory, no steps from experience. Write down every point where you had

The SRAM macro for the OnChipRAM is currently placed right in the center of the north edge DRT is struggling to route at the bottom of the macro (especially at both corners) with some violations. Place the macro closer to the north edge Try to find a better spot. Maybe at the east or west edge?