Top Welcoming Open-Source Verilog Repositories
Top welcoming Verilog repositories. Scored by real 90-day external PR merge rates, maintainer review turnaround speed, and first-time contributor success.
Ranked Verilog Repositories
Showing top 28 of 28 ranked repositories
| Rank | Repository | Tier | Score | Merge Rate | Good First Issues |
|---|---|---|---|---|---|
| #1 | OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/ | A•Welcoming | 67.1 | 59.5% | 1 |
| #2 | FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket | A•Welcoming | 64.8 | 47.2% | 3 |
| #3 | lnis-uofu/OpenFPGA1,133 An Open-source FPGA IP Generator | A•Welcoming | 61.7 | 90.9% | - |
| #4 | Amiga Minimig ported to the Tang Nano 20k FPGA | A•Welcoming | 61.5 | 68.4% | - |
| #5 | analogdevicesinc/hdl1,998 HDL libraries and projects | A•Welcoming | 59.3 | 45.5% | - |
| #6 | A•Welcoming | 59.0 | 89.5% | - | |
| #7 | OpenSTA engine | A•Welcoming | 55.5 | 40.0% | - |
| #8 | OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/ | A•Welcoming | 55.3 | 9.1% | - |
| #9 | Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum! | B•Solid | 49.8 | 100.0% | - |
| #10 | jotego/jt12129 FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10) | B•Solid | 49.6 | 100.0% | - |
| #11 | Greyhound on IHP SG13G2 0.13 μm BiCMOS process | B•Solid | 47.8 | 100.0% | - |
| #12 | najaeda/naja160 Netlist API (and more) for EDA flow development | B•Solid | 46.9 | 65.0% | - |
| #13 | A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 | B•Solid | 46.5 | 33.3% | - |
| #14 | Wren6991/Hazard31,095 3-stage RV32IMACZb* processor with debug | B•Solid | 45.1 | 50.0% | - |
| #15 | Official GIT archive of 1541 ultimate II sources | C•Moderate | 38.7 | 63.1% | - |
| #16 | EttusResearch/uhd1,266 The USRP™ Hardware Driver Repository | D•Risky | 25.6 | 0.0% | - |
| #17 | Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source. | D•Risky | 18.5 | 0.0% | - |
| #18 | XUANTIE-RV/openc9101,479 OpenXuantie - OpenC910 Core | D•Risky | 15.7 | 0.0% | - |
| #19 | 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short). | D•Risky | 13.4 | 0.0% | - |
| #20 | ZipCPU/zipcpu1,574 A small, light weight, RISC CPU soft core | D•Risky | 8.0 | 0.0% | - |
| #21 | Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80. | D•Risky | 8.0 | 0.0% | - |
| #22 | Traces, schematics, and general infos about custom chips reverse-engineered from silicon | D•Risky | 8.0 | 0.0% | - |
| #23 | An AI accelerator implementation with Xilinx FPGA | D•Risky | 8.0 | 0.0% | - |
| #24 | The cheapest, clock-accurate FPGA replacement for PPU, created using reverse engineering. | D•Risky | 8.0 | 0.0% | - |
| #25 | pcileech-fpga with wireless card emulation | D•Risky | 7.5 | 0.0% | - |
| #26 | Full Transformer into a custom chip. microGPT in RTL, generating names on a Virtex-5 FPGA at ~56k tokens/second. | D•Risky | 7.5 | 0.0% | - |
| #27 | An open source library for image processing on FPGA. | D•Risky | 7.5 | 0.0% | - |
| #28 | An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。 | D•Risky | 0.0 | 0.0% | - |
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Frequently Asked Questions: Verilog Open Source
What is the most welcoming Verilog open-source repository?
The highest-ranked Verilog repository on GetMerged is currently The-OpenROAD-Project/OpenROAD, with a C-Rank score of 67.1/100 and a 59.5% PR merge rate.
How can I find good first issues in Verilog?
You can browse verified beginner-friendly issues in Verilog by visiting our curated Good First Issues directory at getmerged.abhishekco.de/good-first-issue/verilog.
What makes a Verilog repository ‘Super Welcoming’ on GetMerged?
A ‘Super Welcoming’ (S-Tier) Verilog repository demonstrates an external PR merge rate above 80%, a median first response time within 24 to 48 hours, active review feedback, and clear onboarding documentation.