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#asic (18 Repositories)

Ranked open-source repositories tagged with #asic, scored by pull request acceptance likelihood and maintainer engagement velocity.

Topic Avg Merge Rate

31.2%

Avg Review Latency

99.1h

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18 repositories tagged #asic

S TierPython 1.2k

siliconcompiler/siliconcompiler

Modular hardware build system

96.7%
Merge Rate
3d
First Review
86%
1st-Timers
6
Maintainers
A TierVEVerilog 160

najaeda/naja

Netlist API (and more) for EDA flow development

92.9%
Merge Rate
22d
First Review
100%
1st-Timers
2
Maintainers
B TierRuby 468

rggen/rggen

Code generation tool for control and status registers

100.0%
Merge Rate
9d
First Review
100%
1st-Timers
1
Maintainers
A TierHAHaskell 1.6k 1 GFIs

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

75.9%
Merge Rate
4d
First Review
67%
1st-Timers
7
Maintainers
B TierASAssembly 3.1k

openhwgroup/cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

26.0%
Merge Rate
3h
First Review
38%
1st-Timers
24
Maintainers
B TierScala 132 4 GFIs

aesc-silicon/ElemRV

ElemRV - End-to-end Open-Source RISC-V Microcontroller

76.5%
Merge Rate
13d
First Review
100%
1st-Timers
1
Maintainers
B TierPython 285

FPGA-Research/FABulous

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

25.0%
Merge Rate
11h
First Review
33%
1st-Timers
11
Maintainers
B TierC++ 239

masc-ucsc/livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

68.2%
Merge Rate
-
First Review
33%
1st-Timers
0
Maintainers
D TierScala 1.4k

ucb-bar/gemmini

Berkeley's Spatial Array Generator

0.0%
Merge Rate
23d
First Review
0%
1st-Timers
1
Maintainers
D TierScala 399

tensil-ai/tensil

Open source machine learning accelerators

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierC 422

sld-columbia/esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierPython 407

cornell-zhang/allo

Allo Accelerator Design and Programming Framework (PLDI'24)

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierVEVerilog 362

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierVEVerilog 229

furrtek/SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierC 327

pulp-platform/mempool

A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierPython 340

unihd-cag/skillbridge

A seamless python to Cadence Virtuoso Skill interface

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierJava 1.0k

esig/dss

Digital Signature Service : creation, extension and validation of advanced electronic signatures

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierVEVerilog 264

openecos-projects/icsprout55-pdk

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
Best Asic Open Source Repositories & C-Rank™ | GetMerged