#asic (25 Repositories)
Ranked open-source repositories tagged with #asic, scored by pull request acceptance likelihood and maintainer engagement velocity.
40.5%
70.8h
25 repositories tagged #asic
siliconcompiler/siliconcompiler
Modular hardware build system
keplertech/kepler-formal
Digital Design Equivalence Checking
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
librelane/librelane
ASIC implementation flow infrastructure, successor to OpenLane
FPGA-Research/FABulous
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
SystemRDL/PeakRDL
Control and status register code generator toolchain
rggen/rggen
Code generation tool for control and status registers
aesc-silicon/ElemRV
ElemRV - End-to-end Open-Source RISC-V Microcontroller
cornell-zhang/allo
Allo Accelerator Design and Programming Framework (PLDI'24)
najaeda/naja
Netlist API (and more) for EDA flow development
SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
sld-columbia/esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
masc-ucsc/livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
openhwfoundation/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
openecos-projects/icsprout55-pdk
55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).
furrtek/SiliconRE
Traces, schematics, and general infos about custom chips reverse-engineered from silicon
tensil-ai/tensil
Open source machine learning accelerators
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
pulp-platform/mempool
A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
unihd-cag/skillbridge
A seamless python to Cadence Virtuoso Skill interface
ucb-bar/gemmini
Berkeley's Spatial Array Generator
esig/dss
Digital Signature Service : creation, extension and validation of advanced electronic signatures