Contributor Matchmaker
Best Verilog Repos to Contribute To
Matched to your experience level using real merge rates, maintainer response times, and first-PR success data.
57% matchA Tier 1 GFIs
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
- Active in the last month
51% matchA Tier
lnis-uofu/OpenFPGA
An Open-source FPGA IP Generator
- Merges 91% of outside pull requests
49% matchB Tier
jotego/jt12
FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
- Merges 100% of outside pull requests
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