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Best Verilog Repos to Contribute To

Matched to your experience level using real merge rates, maintainer response times, and first-PR success data.

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40% matchA Tier 3 GFIs

jotego/jtcores

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

  • 60% of first-time PRs get merged
  • 3 open good first issues
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33% matchA Tier 1 GFIs

The-OpenROAD-Project/OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  • 65% of first-time PRs get merged
  • 1 open good first issues
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