#verilog (30 Repositories)
Ranked open-source repositories tagged with #verilog, scored by pull request acceptance likelihood and maintainer engagement velocity.
43.9%
55.3h
30 repositories tagged #verilog
siliconcompiler/siliconcompiler
Modular hardware build system
FPGAwars/apio
:seedling: Open source ecosystem for open FPGA boards
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
najaeda/naja
Netlist API (and more) for EDA flow development
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
rggen/rggen
Code generation tool for control and status registers
cocotb/cocotb
cocotb: Python-based chip (RTL) verification
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
SpinalHDL/SpinalHDL
Scala based HDL
google/xls
XLS: Accelerated HW Synthesis
The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
FPGA-Research/FABulous
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
zachjs/sv2v
SystemVerilog to Verilog conversion
lcapossio/fpgacapZero
fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI
tommythorn/Reduceron
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
Eriemon/verilog-generator
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
ymherklotz/verismith
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
loykylewong/FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
dalance/sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
mshr-h/vscode-verilog-hdl-support
Verilog/SystemVerilog support for VS Code
0BAB1/HOLY_CORE_COURSE
Learn how to build our own RV32I(M) core, verify it and actually use it FOR FREE (.md tutorials). From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Hanley-Yao/Zynq7010_eink_controller
这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
circuitvalley/USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
esonghori/TinyGarble
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
zangman/de10-nano
Absolute beginner's guide to the de10-nano