#verilog (30 Repositories)
Ranked open-source repositories tagged with #verilog, scored by pull request acceptance likelihood and maintainer engagement velocity.
70.0%
51.2h
30 repositories tagged #verilog
siliconcompiler/siliconcompiler
Modular hardware build system
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
FPGAwars/apio
:seedling: Open source ecosystem for open FPGA boards
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
google/xls
XLS: Accelerated HW Synthesis
MikePopoloski/slang
SystemVerilog compiler and language services
analogdevicesinc/hdl
HDL libraries and projects
cocotb/cocotb
cocotb: Python-based chip (RTL) verification
FPGA-Research/FABulous
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
dalance/svls
SystemVerilog language server
SpinalHDL/SpinalHDL
Scala based HDL
rggen/rggen
Code generation tool for control and status registers
chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
0BAB1/HOLY_CORE_COURSE
Learn how to build our own RV32I(M) core, verify it and actually use it FOR FREE (.md tutorials). From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
hdl/awesome
A curated list of awesome resources for HDL design and verification
FPGAwars/icestudio
:snowflake: Visual editor for open FPGA boards
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
zangman/de10-nano
Absolute beginner's guide to the de10-nano
nickg/nvc
VHDL compiler and simulator
lcapossio/fpgacapZero
fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI
najaeda/naja
Netlist API (and more) for EDA flow development
dalance/sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
zachjs/sv2v
SystemVerilog to Verilog conversion
circuitvalley/USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
dalance/svlint
SystemVerilog linter