#systemverilog (17 Repositories)
Ranked open-source repositories tagged with #systemverilog, scored by pull request acceptance likelihood and maintainer engagement velocity.
47.9%
46.9h
17 repositories tagged #systemverilog
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
hudson-trading/slang-server
A SystemVerilog language server based on the Slang library.
rggen/rggen
Code generation tool for control and status registers
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
chipsalliance/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
zachjs/sv2v
SystemVerilog to Verilog conversion
intel/rohd-hcl
A hardware component library developed with ROHD.
loykylewong/FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
Nic30/hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
mshr-h/vscode-verilog-hdl-support
Verilog/SystemVerilog support for VS Code
dalance/svlint
SystemVerilog linter
dalance/sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
vproc/vicuna
RISC-V Zve32x Vector Coprocessor
pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6