#rtl (26 Repositories)
Ranked open-source repositories tagged with #rtl, scored by pull request acceptance likelihood and maintainer engagement velocity.
31.2%
33.8h
26 repositories tagged #rtl
siliconcompiler/siliconcompiler
Modular hardware build system
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
MahdiMajidzadeh/bootstrap-v4-rtl
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
rggen/rggen
Code generation tool for control and status registers
SpinalHDL/SpinalHDL
Scala based HDL
The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
intel/rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chipsalliance/rocket-chip
Rocket Chip Generator
ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
mit-han-lab/spatten
[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
appica-dev/appica-ui
A beautifully styled UI component library for building accessible, modern web applications and scalable design systems.
ucsc-vama/essent
high-performance RTL simulator
ucb-bar/constellation
A Chisel RTL generator for network-on-chip interconnects
SpinalHDL/SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
blarney-lang/blarney
Haskell library for hardware description
Eriemon/verilog-generator
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
shraga100/claude-desktop-rtl-patch
CSS patch for Claude Desktop windows version to enable RTL (right-to-left) support for Hebrew and Arabic
bu-icsg/dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
mortezakarimi/gentelella-rtl
Free RTL Bootstrap 3 Admin Template
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
erfanmola/DontAskToAsk
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