#riscv (27 Repositories)
Ranked open-source repositories tagged with #riscv, scored by pull request acceptance likelihood and maintainer engagement velocity.
22.0%
30.4h
27 repositories tagged #riscv
esp-rs/esp-pacs
Peripheral Access Crates for Espressif SoCs and modules
libriscv/libriscv
The fastest RVA23 RISC-V sandbox
rustsbi/rustsbi
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see prototyper folder.
nervosnetwork/ckb-vm
CKB's vm, based on open source RISC-V ISA
GaloisInc/macaw
Open source binary analysis tools.
riscv/riscv-unified-db
Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools
diodesign/diosix
A lightweight, robust, multiprocessor bare-metal hypervisor written in Zig for RISC-V
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chipsalliance/rocket-chip
Rocket Chip Generator
ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
SpinalHDL/SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
riscv-software-src/homebrew-riscv
homebrew (macOS) packages for RISC-V toolchain
QQxiaoming/quard_star_tutorial
This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development board. 本项目旨在真正从0开始构建嵌入式linux系统，为了剖析芯片从上电开始执行第一条指令到整个系统运行，基于qemu定制模拟器开发板。
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
bu-icsg/dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
fnuecke/sedna
Sedna - a pure Java RISC-V emulator.
sysprog21/semu
A minimalist RISC-V system emulator capable of running Linux kernel with efficient event-driven scheduling
Wren6991/Hazard3
3-stage RV32IMACZb* processor with debug
pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Rompass/openc6-bios
An open-source RISC-V firmware platform for ESP32-C6(8MB Flash). Implements a BIOS/Payload architecture with a custom system call interface (ABI), independent LP-Core coprocessor management, and an anti-brick A/B OTA system.
carlosedp/chiselv
A RISC-V Core (RV32I) written in Chisel HDL
mrLSD/riscv-fs
F# RISC-V Instruction Set formal specification
sld-columbia/esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
d0iasm/rvemu-for-book
Reference implementation for the book "Writing a RISC-V Emulator in Rust".
0BAB1/HOLY_CORE_COURSE
Learn how to build our own RV32I(M) core, verify it and actually use it FOR FREE (.md tutorials). From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
sifiveinc/freedom-u-sdk
Freedom U Software Development Kit (FUSDK)