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#hdl (16 Repositories)

Ranked open-source repositories tagged with #hdl, scored by pull request acceptance likelihood and maintainer engagement velocity.

Topic Avg Merge Rate

47.8%

Avg Review Latency

13.4h

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16 repositories tagged #hdl

S TierRust 1.0k

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

91.3%
Merge Rate
-
First Review
75%
1st-Timers
8
Maintainers
B TierPython 2.1k

amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

85.7%
Merge Rate
8h
First Review
100%
1st-Timers
3
Maintainers
A TierVEVerilog 2.0k

analogdevicesinc/hdl

HDL libraries and projects

45.5%
Merge Rate
-
First Review
50%
1st-Timers
8
Maintainers
B TierDart 492

intel/rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

58.2%
Merge Rate
3d
First Review
75%
1st-Timers
4
Maintainers
B TierShell 179 1 GFIs

hdl/awesome

A curated list of awesome resources for HDL design and verification

100.0%
Merge Rate
-
First Review
100%
1st-Timers
0
Maintainers
B TierShell 477

analogdevicesinc/plutosdr-fw

PlutoSDR Firmware

100.0%
Merge Rate
18h
First Review
0%
1st-Timers
1
Maintainers
B TierC++ 122

openlab-x/OpenCircuitX

Free, open-source EDA platform for VHDL and Verilog. HDL editor, circuit canvas, RTL viewer, waveform viewer, and FPGA toolchain in one window.

100.0%
Merge Rate
3d
First Review
0%
1st-Timers
1
Maintainers
B TierGo 2.4k

langhuihui/monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

50.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
B TierC++ 242

masc-ucsc/livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

70.0%
Merge Rate
-
First Review
33%
1st-Timers
0
Maintainers
B TierLELean 105

Verilean/sparkle

A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.

64.0%
Merge Rate
2d
First Review
0%
1st-Timers
0
Maintainers
D TierC++ 130

asyncvlsi/act

ACT hardware description language and core tools.

0.0%
Merge Rate
-
First Review
0%
1st-Timers
1
Maintainers
D TierC++ 331

Kitware/VeloView

VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierVEVerilog 229

furrtek/SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierRust 129

pc2/sus-compiler

A new Hardware Design Language that keeps you in the driver's seat

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierScala 400

tensil-ai/tensil

Open source machine learning accelerators

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierC++ 263

kactus2/kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
Best Hdl Open Source Repositories & C-Rank™ | GetMerged