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#fpga (30 Repositories)

Ranked open-source repositories tagged with #fpga, scored by pull request acceptance likelihood and maintainer engagement velocity.

Topic Avg Merge Rate

55.9%

Avg Review Latency

45.7h

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30 repositories tagged #fpga

S TierVEVerilog 1.1k

lnis-uofu/OpenFPGA

An Open-source FPGA IP Generator

95.0%
Merge Rate
9h
First Review
100%
1st-Timers
4
Maintainers
S TierPython 1.2k

siliconcompiler/siliconcompiler

Modular hardware build system

96.7%
Merge Rate
3d
First Review
86%
1st-Timers
6
Maintainers
S TierPython 1.0k

FPGAwars/apio

:seedling: Open source ecosystem for open FPGA boards

93.3%
Merge Rate
11h
First Review
100%
1st-Timers
2
Maintainers
A TierC++ 1.3k

verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

86.0%
Merge Rate
22h
First Review
88%
1st-Timers
19
Maintainers
A TierC++ 1.7k 1 GFIs

trabucayre/openFPGALoader

Universal utility for programming FPGA

100.0%
Merge Rate
21h
First Review
100%
1st-Timers
2
Maintainers
A TierVEVerilog 160

najaeda/naja

Netlist API (and more) for EDA flow development

92.9%
Merge Rate
22d
First Review
100%
1st-Timers
2
Maintainers
A TierC++ 681

Xilinx/XRT

Run Time for AIE and FPGA based platforms

86.0%
Merge Rate
6d
First Review
90%
1st-Timers
16
Maintainers
B TierRuby 468

rggen/rggen

Code generation tool for control and status registers

100.0%
Merge Rate
9d
First Review
100%
1st-Timers
1
Maintainers
A TierC# 140

one-ware/OneWare

Next Generation IDE for Electronics Development

74.6%
Merge Rate
2d
First Review
83%
1st-Timers
2
Maintainers
A TierTCTcl 406

pavel-demin/red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

100.0%
Merge Rate
1d
First Review
100%
1st-Timers
2
Maintainers
A TierHAHaskell 1.6k 1 GFIs

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

75.9%
Merge Rate
4d
First Review
67%
1st-Timers
7
Maintainers
B TierScala 2.0k

SpinalHDL/SpinalHDL

Scala based HDL

70.0%
Merge Rate
2d
First Review
89%
1st-Timers
10
Maintainers
B TierASAssembly 3.1k

openhwgroup/cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

26.0%
Merge Rate
3h
First Review
38%
1st-Timers
24
Maintainers
B TierC++ 318

simoninns/DomesdayDuplicator

High-speed LaserDisc RF sampler

100.0%
Merge Rate
-
First Review
0%
1st-Timers
1
Maintainers
B TierShell 115

openXC7/toolchain-installer

Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7

100.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
B TierPython 285

FPGA-Research/FABulous

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

25.0%
Merge Rate
11h
First Review
33%
1st-Timers
11
Maintainers
B TierScala 167

LoveLonelyTime/Bergamot

An exquisite superscalar RV32GC processor.

100.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
B TierDart 347

Midstall/aegis

Open source FPGA silicon

87.5%
Merge Rate
-
First Review
100%
1st-Timers
0
Maintainers
B TierC++ 239

masc-ucsc/livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

68.2%
Merge Rate
-
First Review
33%
1st-Timers
0
Maintainers
B TierPython 106

lcapossio/fpgacapZero

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

100.0%
Merge Rate
5d
First Review
0%
1st-Timers
1
Maintainers
D TierScala 136

loykylewong/FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierPython 222

Eriemon/verilog-generator

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierHAHaskell 461

tommythorn/Reduceron

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierScala 399

tensil-ai/tensil

Open source machine learning accelerators

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierShell 273

zangman/de10-nano

Absolute beginner's guide to the de10-nano

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierVEVerilog 2.0k

analogdevicesinc/hdl

HDL libraries and projects

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierC 441

tillitis/tillitis-key1

FPGA verilog and firmware for TKey, the flexible and open USB security key 🔑

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierVEVerilog 1.4k

chili-chips-ba/wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierScala 132

antmicro/fastvdma

Antmicro's fast, vendor-neutral DMA IP in Chisel

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierShell 275

embedeep/Free-TPU

Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.

0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
Best Fpga Open Source Repositories & C-Rank™ | GetMerged