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#fpga (30 Repositories)

Ranked open-source repositories tagged with #fpga, scored by pull request acceptance likelihood and maintainer engagement velocity.

Topic Avg Merge Rate

74.3%

Avg Review Latency

15.0h

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30 repositories tagged #fpga

S TierPython 1.2k

siliconcompiler/siliconcompiler

Modular hardware build system

91.6%
Merge Rate
2d
First Review
86%
1st-Timers
4
Maintainers
S TierPython 2.2k

GlasgowEmbedded/glasgow

Scots Army Knife for electronics

84.2%
Merge Rate
15h
First Review
86%
1st-Timers
15
Maintainers
A TierC++ 1.3k

verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

79.2%
Merge Rate
-
First Review
86%
1st-Timers
16
Maintainers
A TierC++ 110

keplertech/kepler-formal

Digital Design Equivalence Checking

66.7%
Merge Rate
11h
First Review
67%
1st-Timers
6
Maintainers
A TierPython 1.0k

FPGAwars/apio

:seedling: Open source ecosystem for open FPGA boards

78.6%
Merge Rate
-
First Review
100%
1st-Timers
4
Maintainers
A TierPython 596 1 GFIs

spcl/dace

DaCe - Data Centric Parallel Programming

60.0%
Merge Rate
1d
First Review
64%
1st-Timers
10
Maintainers
A TierVEVerilog 314 3 GFIs

jotego/jtcores

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

47.2%
Merge Rate
-
First Review
60%
1st-Timers
26
Maintainers
A TierC++ 323

Domesday86/DomesdayDuplicator

High-speed LaserDisc RF sampler

100.0%
Merge Rate
13h
First Review
100%
1st-Timers
2
Maintainers
A TierC++ 692

Xilinx/XRT

Run Time for AIE and FPGA based platforms

82.5%
Merge Rate
-
First Review
79%
1st-Timers
22
Maintainers
A TierHAHaskell 1.6k 1 GFIs

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

71.6%
Merge Rate
-
First Review
83%
1st-Timers
9
Maintainers
B TierPython 2.1k

amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

85.7%
Merge Rate
8h
First Review
100%
1st-Timers
3
Maintainers
A TierVEVerilog 1.1k

lnis-uofu/OpenFPGA

An Open-source FPGA IP Generator

90.9%
Merge Rate
-
First Review
100%
1st-Timers
4
Maintainers
A TierVEVerilog 2.0k

analogdevicesinc/hdl

HDL libraries and projects

45.5%
Merge Rate
-
First Review
50%
1st-Timers
8
Maintainers
B TierC 443

tillitis/tillitis-key1

FPGA verilog and firmware for TKey, the flexible and open USB security key 🔑

66.7%
Merge Rate
5h
First Review
67%
1st-Timers
3
Maintainers
A TierPython 305 1 GFIs

FPGA-Research/FABulous

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

33.3%
Merge Rate
-
First Review
33%
1st-Timers
11
Maintainers
B TierScala 110

carlosedp/chiselv

A RISC-V Core (RV32I) written in Chisel HDL

100.0%
Merge Rate
<1h
First Review
100%
1st-Timers
2
Maintainers
A TierASAssembly 3.1k

openhwgroup/cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

25.4%
Merge Rate
6h
First Review
40%
1st-Timers
29
Maintainers
B TierPython 210

SystemRDL/PeakRDL

Control and status register code generator toolchain

100.0%
Merge Rate
<1h
First Review
100%
1st-Timers
1
Maintainers
B TierC++ 318

simoninns/DomesdayDuplicator

High-speed LaserDisc RF sampler

100.0%
Merge Rate
11h
First Review
100%
1st-Timers
1
Maintainers
B TierScala 2.1k

SpinalHDL/SpinalHDL

Scala based HDL

57.6%
Merge Rate
-
First Review
71%
1st-Timers
4
Maintainers
B TierC++ 349

ferrandi/PandA-bambu

PandA-bambu public repository

58.3%
Merge Rate
8h
First Review
100%
1st-Timers
2
Maintainers
B TierJava 391

Xilinx/RapidWright

Build Customized FPGA Implementations for Vivado

25.0%
Merge Rate
8h
First Review
33%
1st-Timers
4
Maintainers
B TierC++ 1.8k 1 GFIs

trabucayre/openFPGALoader

Universal utility for programming FPGA

57.1%
Merge Rate
4h
First Review
0%
1st-Timers
4
Maintainers
B TierRuby 471

rggen/rggen

Code generation tool for control and status registers

100.0%
Merge Rate
9d
First Review
100%
1st-Timers
1
Maintainers
B TierTCTcl 406

pavel-demin/red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

100.0%
Merge Rate
1d
First Review
100%
1st-Timers
2
Maintainers
B TierPython 492

0BAB1/HOLY_CORE_COURSE

Learn how to build our own RV32I(M) core, verify it and actually use it FOR FREE (.md tutorials). From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.

100.0%
Merge Rate
2h
First Review
100%
1st-Timers
2
Maintainers
B TierShell 477

analogdevicesinc/plutosdr-fw

PlutoSDR Firmware

100.0%
Merge Rate
18h
First Review
0%
1st-Timers
1
Maintainers
B TierJavaScript 1.9k

FPGAwars/icestudio

:snowflake: Visual editor for open FPGA boards

71.4%
Merge Rate
2h
First Review
50%
1st-Timers
1
Maintainers
B TierC 4.8k

open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

50.0%
Merge Rate
6h
First Review
100%
1st-Timers
0
Maintainers
B TierVEVerilog 1.4k

chili-chips-ba/wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

100.0%
Merge Rate
9h
First Review
0%
1st-Timers
2
Maintainers
Best Fpga Open Source Repositories & C-Rank™ | GetMerged