Topic Hub
#vhdl (8 Repositories)
Ranked open-source repositories tagged with #vhdl, scored by pull request acceptance likelihood and maintainer engagement velocity.
Topic Avg Merge Rate
54.8%
Avg Review Latency
43.4h
Filter by language
8 repositories tagged #vhdl
S TierPython 1.2k
siliconcompiler/siliconcompiler
Modular hardware build system
96.7%
Merge Rate
3d
First Review
86%
1st-Timers
6
Maintainers
A TierPython 2.5k 1 GFIs
cocotb/cocotb
cocotb: Python-based chip (RTL) verification
70.9%
Merge Rate
20h
First Review
69%
1st-Timers
20
Maintainers
A TierHAHaskell 1.6k 1 GFIs
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
75.9%
Merge Rate
4d
First Review
67%
1st-Timers
7
Maintainers
B TierScala 2.0k
SpinalHDL/SpinalHDL
Scala based HDL
70.0%
Merge Rate
2d
First Review
89%
1st-Timers
10
Maintainers
B TierPython 285
FPGA-Research/FABulous
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
25.0%
Merge Rate
11h
First Review
33%
1st-Timers
11
Maintainers
B TierPython 106
lcapossio/fpgacapZero
fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI
100.0%
Merge Rate
5d
First Review
0%
1st-Timers
1
Maintainers
D TierVHVHDL 2.9k
ghdl/ghdl
VHDL 2008/93/87 simulator
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierC++ 332
Nic30/hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers