Topic Hub
#systemverilog-parser (2 Repositories)
Ranked open-source repositories tagged with #systemverilog-parser, scored by pull request acceptance likelihood and maintainer engagement velocity.
Topic Avg Merge Rate
38.3%
Avg Review Latency
1.3h
Filter by language
Rankings/rankings/cpp
2 repositories tagged #systemverilog-parser
A TierC++ 1.9k
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
76.7%
Merge Rate
3h
First Review
67%
1st-Timers
8
Maintainers
D TierC++ 332
Nic30/hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers