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#high-level-synthesis (7 Repositories)
Ranked open-source repositories tagged with #high-level-synthesis, scored by pull request acceptance likelihood and maintainer engagement velocity.
Topic Avg Merge Rate
9.5%
Avg Review Latency
0.8h
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7 repositories tagged #high-level-synthesis
B TierC++ 1.8k
google/xls
XLS: Accelerated HW Synthesis
66.7%
Merge Rate
5h
First Review
22%
1st-Timers
17
Maintainers
D TierScala 152
cucapra/dahlia
Time-sensitive affine types for predictable hardware generation
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierPython 338
cornell-zhang/heterocl
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierPython 407
cornell-zhang/allo
Allo Accelerator Design and Programming Framework (PLDI'24)
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierC++ 343
definelicht/hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierRust 610
calyxir/calyx
Intermediate Language (IL) for Hardware Accelerator Generators
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierC++ 340
changwoolee/lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers