Topic Hub
#hardware-description-language (6 Repositories)
Ranked open-source repositories tagged with #hardware-description-language, scored by pull request acceptance likelihood and maintainer engagement velocity.
Topic Avg Merge Rate
50.8%
Avg Review Latency
36.8h
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6 repositories tagged #hardware-description-language
A TierHAHaskell 1.6k 1 GFIs
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
71.6%
Merge Rate
1d
First Review
83%
1st-Timers
9
Maintainers
B TierPython 210
SystemRDL/PeakRDL
Control and status register code generator toolchain
100.0%
Merge Rate
<1h
First Review
100%
1st-Timers
1
Maintainers
B TierC++ 287
SystemRDL/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
100.0%
Merge Rate
8d
First Review
0%
1st-Timers
1
Maintainers
B TierPython 751
JulianKemmerer/PipelineC
PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
33.3%
Merge Rate
-
First Review
0%
1st-Timers
1
Maintainers
D TierC++ 130
asyncvlsi/act
ACT hardware description language and core tools.
0.0%
Merge Rate
-
First Review
0%
1st-Timers
1
Maintainers
D TierRust 126
pc2/sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers