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#firrtl (4 Repositories)
Ranked open-source repositories tagged with #firrtl, scored by pull request acceptance likelihood and maintainer engagement velocity.
Topic Avg Merge Rate
20.6%
Avg Review Latency
2.7h
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Rankings/rankings/scala
4 repositories tagged #firrtl
A TierScala 4.8k
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
82.3%
Merge Rate
11h
First Review
82%
1st-Timers
11
Maintainers
D TierScala 123
freechipsproject/diagrammer
Provides dot visualizations of chisel/firrtl circuits
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierScala 747
chipsalliance/firrtl
Flexible Intermediate Representation for RTL
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers
D TierScala 195
ucsc-vama/essent
high-performance RTL simulator
0.0%
Merge Rate
-
First Review
0%
1st-Timers
0
Maintainers