MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy Version!
C-Rank Grade: D (Risky) - 8/100
External PR Merge Rate: -
Response Time: -
First Timer Success: -
circuitvalley/mipi_csi_receiver_FPGA has a recorded first-timer success rate of 0.0%. Repositories ranked D typically provide actionable feedback during code reviews and actively nurture new community contributors.
Maintainers in circuitvalley/mipi_csi_receiver_FPGA respond to incoming external pull requests in approximately 0.0 hours on average. Keeping PRs focused on single tasks and ensuring tests pass helps maintainers review faster.
The C-Rank™ system evaluates GitHub projects on a 0–100 scale using real data: PR merge rates, review turnaround time, active maintainer presence, and first-time contributor success. A score of 8.0 places circuitvalley/mipi_csi_receiver_FPGA in the D tier.
The external contributor pull request merge rate for circuitvalley/mipi_csi_receiver_FPGA is 0.0%, based on public PR activity from non-core contributors.
circuitvalley/mipi_csi_receiver_FPGA does not currently have active "good first issue" tags indexed, but accepts external contributions through standard GitHub issue tracking.
MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy Version!
Collaborative maintainer environment in circuitvalley/mipi_csi_receiver_FPGA. Reviews community pull requests with focus on project quality.
Discussions in circuitvalley/mipi_csi_receiver_FPGA focus heavily on practical implementation feedback, code formatting standards, and issue reproduction details.
Unlinked PRs without issue context and changes that fail automated test suites face the highest review friction.
Average Response Latency
Tracks hours until a maintainer leaves a review, comment, or PR response.
External Acceptance Rate
Percentage of community pull requests successfully merged into main.
First PR Conversion
Rate at which developers submitting their first repository PR succeed.
Show contributors that your repository actively reviews and merges external pull requests.
[](https://getmerged.abhishekco.de/circuitvalley/mipi_csi_receiver_FPGA?utm_source=github&utm_medium=badge)
External PR acceptance
First PR success rate
50% receive response in
90% receive response in
Maintainer review activity heatmap
Maintainer Strategy: Maintainer Sweet Spot: PRs under 150 lines merge in ~16 hours (81% approval). Large PRs (>500 lines) take ~115 hours (29% approval). Keep your diff compact for rapid review.
No cached good first issues currently tracked for circuitvalley/mipi_csi_receiver_FPGA.
Rate what actually matters after opening a pull request here.
Rate your first-hand PR experience (review speed, maintainer responsiveness, and onboarding ease) to help other contributors.
When evaluating whether to contribute to circuitvalley/mipi_csi_receiver_FPGA, response velocity and maintainer engagement are crucial. GetMerged continuously tracks pull request trajectories, first-comment latency, and code review rounds to help developers avoid submitting pull requests to backlogged repositories.
Currently, maintainers of circuitvalley/mipi_csi_receiver_FPGA acknowledge new external contributions in approximately -. Out of all submitted pull requests from non-core authors in the last 180-day window, 0.0% were successfully merged into the primary branch.
circuitvalley/mipi_csi_receiver_FPGA has a recorded first-timer success rate of 0.0%. Repositories ranked Risky typically provide actionable feedback during code reviews and actively nurture new community contributors.
The initial maintainer response time averages ~-. Keeping PRs scoped to single concerns and ensuring CI checks succeed will optimize review turnaround.
The C-Rank™ index scores repositories on a 0 to 100 scale using an objective formula: external PR merge rates, initial response speed, active maintainer count, and first-time contributor retention. A score of 8.0 places circuitvalley/mipi_csi_receiver_FPGA in the Risky tier.
The external pull request merge rate is 0.0%. GetMerged isolates non-core community contributions so external developers get an accurate benchmark of PR acceptance probability.
circuitvalley/mipi_csi_receiver_FPGA does not have open beginner labels indexed currently, but external PRs for bugs and documentation improvements are evaluated via normal issue triage.
All metrics displayed for circuitvalley/mipi_csi_receiver_FPGA are automatically retrieved via the public GitHub API and recalculated daily. Insider pull requests submitted by repository owners or organization members are excluded from merge rate calculations to preserve objective external contributor statistics.