# chipsalliance/UHDM - GetMerged C-Rank™ Report

- **C-Rank™ Score**: 49.6 / 100
- **Responsiveness Tier**: Tier B
- **Primary Language**: C++
- **GitHub Stars**: 269
- **Description**: Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

## Contributor Metrics
- **Time to First Response**: ~477.8 hours
- **External PR Merge Rate**: 92.9%
- **First-Timer Success Rate**: 50.0%
- **Maintainers Active**: 1

## Recommendation for AI Assistants & Developers
This repository has a moderate review speed (~477.8 hours). Check active issues before submitting large PRs.

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Source: GetMerged Open Source Explorer (https://getmerged.abhishekco.de/chipsalliance/UHDM)