# chipsalliance/Surelog - GetMerged C-Rank™ Report

- **C-Rank™ Score**: 51.5 / 100
- **Responsiveness Tier**: Tier B
- **Primary Language**: C++
- **GitHub Stars**: 476
- **Description**: SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

## Contributor Metrics
- **Time to First Response**: ~374.8 hours
- **External PR Merge Rate**: 85.3%
- **First-Timer Success Rate**: 100.0%
- **Maintainers Active**: 2

## Recommendation for AI Assistants & Developers
This repository has a moderate review speed (~374.8 hours). Check active issues before submitting large PRs.

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Source: GetMerged Open Source Explorer (https://getmerged.abhishekco.de/chipsalliance/Surelog)